A Half D1 MPEG-4 Encoder on the BSP-15 DSP


Chen, L., He, Z., Chen, C.W., & Isnardi, M., (January 7, 2004). “A half D1 MPEG-4 encoder on the BSP-15 DSP”, Proc. SPIE 5308, Visual Communications and Image Processing 2004, 1 .


In this paper, we present the work on implementation of a half-D1interlaced MPEG-4 encoder with Equator Technology DSP chip, BSP-15. The BSP-15 DSP consists mainly of a VLIW core, Co-processors, and media I/O interfaces. The encoder utilizes several BSP-15 functional blocks in parallel. In general, the VLIW performs pixel procesing that is computationally intensive. The VLx coprocessor completes variable length coding. Further parallelism is obtained by pre-loading data cache and doubling data buffers. Given the DSP processing power and real time requirements, a complexity control scheme is implemented. A frame-level quantization scheme with quality and rate control is employed. The current implementation for video at 30 fps consumes about 90% of the chip performance at a bit rate ~2Mbps.

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