Yices 2.2


Dutertre, B. (2014, 18-22 July ). Yices 2.2. Paper presented at the International Conference on Computer Aided Verification (CAV’14), Vienna, Austria.


Yices is an SMT solver developed by SRI International. The first version of Yices was released in 2006 and has been continuously updated since then. In 2007, we started a complete re-implementation of the solver to improve performance and increase modularity and flexibility. We describe the latest release of Yices, namely, Yices 2.2. We present the tool’s architecture and discuss the algorithms it implements, and we describe recent developments such as support for the SMT-LIB 2.0 notation and various performance improvements.

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