Wafer level packaging with soldered stress engineered micro-springs


Chow, E. M.; Fork, D. K.; Chua, C. L.; Van Schuylenbergh, K.; Hantschel, T. Wafer level packaging with soldered stress engineered micro-springs. IEEE Transactions on Advanced Packaging. 2009 May; 32 (2): 372-378.


Micro springs for integrated circuit test and packaging are demonstrated as soldered flip chip interconnects in a direct die to printed circuit board package. The spring interconnects are fabricated with thin film metallization as the last step in a wafer-scale process. The z-compliance of the interconnects can be used to test and/or burn-in parts in wafer form. After the parts are diced from the wafer, the springs then become the first-level (and often the last-level) interconnect between the chip and the board. The xy-compliance of the interconnect enables considerably large die to be soldered to an organic printed circuit board without underfill using an SMT compatible process. To demonstrate this concept, daisy chain test vehicles were fabricated on die measuring 11.5 mm by 6.5 mm with 48 spring contacts on a 0.8 mm by 0.65 mm grid array, each spring measuring 400 m by 100 m. The parts were placed onto organic boards with screen printed solder paste using a pick and place machine. The parts were reflowed to complete the solder connection to each spring using eutectic and lead-free solder. Assembled parts have undergone >20,000 hot plate thermal cycles and >1000 oven thermal cycles without failure.

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