Fast, Full Chip Image Stitching of Nanoscale Integrated Circuits

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David Zhang, Gooitzen van der Wal, Phil Miller, David Stoker, Erik Matlin, Naveen Marri, Gary Gan, Joe Zhang, Jane Asmuth, Sek Chai, David Weaver, Scott Silverman, Michael DiBattista, Robert Chivas, Christopher G. L. Ferri, David Taylor, Jordan Furlong, Thomas Harper, Dustin Kobs, “Fast, Full Chip Image Stitching of Nanoscale Integrated Circuits”, March 25-28, 2019.


The rapid progression of semiconductor technology has significantly impacted the ability to examine and analyze complex integrated circuits (ICs). Small device feature sizes, combined with large die sizes, add a heavy processing burden that severely limits our timely ability to perform defect validation and anti-tampering analysis at full scale. In this paper, we describe the algorithmic steps taken in the processing pipeline to quickly create a global image database of an entire advanced IC. We focused specifically on the image alignment and stitching algorithms necessary to support a combined field-of-view of a given layer of a die. We describe key algorithmic challenges such as contextual semantics that limits the robustness of the alignment algorithm. We also describe the use of database indexing to manage and traverse the enormous amounts of data.

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