Dynamic LDPC Codes for Nanoscale Memory with Varying Fault Arrival Rates



Modern state-of-the-art nanodevices exhibit remarkable electronic properties, but the current assembly techniques yield very high defect and fault rates. Static errors can be addressed at fabrication time by testing and reconfiguration, but soft errors are problematic since their arrival rates are expected to vary over the lifetime of a part. Usual designs consider error correcting codes that tolerate the maximum failure rate expected over the entire lifetime. In this paper, we propose using a special variant of low-density parity codes (LDPCs) – Euclidean Geometry LDPC (EG-LDPC) codes – to enable dynamic changes in the level of fault tolerance. EG-LDPC codes have high error correcting ability (for large words they can approach the optimal Shannon limit) and they are sparse (circuit implementation requires small fan-in). In addition, a special property of EG-LDPC codes enables us to dynamically adjust the error correcting capacity for improved system performance (e.g., lower power consumption) during periods of expected low fault arrival rate. We present a system architecture for nanomemory based on nanoPLA building blocks using EG-LDPCs, where the encoder/decoder could also have faults, and analyze the fault detection and correction capabilities considering dynamic fault tolerance.

Keywords: Error correction codes, Decoding, Parity check codes, Logic gates, Circuit faults, Encoding, Geometry

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