Disordered nanowire based photovoltaics


Raychaudhuri, S.; Lujan, R. A.; Song, K. W.; Paulson, C.; Street, R. A. Disordered nanowire based photovoltaics. 2011 Spring Meeting of the Materials Research Society; 2011 April 25-29; San Francisco, CA.


In planar photovoltaic structures increasing the device thickness will increase the absorption efficiency of the material but will reduce the carrier collection efficiency. Vertical solar cells provide a means to circumvent this trade-off, but also pose a considerable manufacturing challenge. In this paper we present experimental results incorporating traditional amorphous silicon (a-Si) photovoltaic devices with a three-dimensional, disordered nanowire (NW) mat using approaches that are compatible with current large area a-Si processing techniques. We are able to grow disordered mats on a variety of substrates including silicon, glass and flexible stainless steel foil. We have devised a scheme where a thin a-Si cell is deposited over a disordered NW mat. The disordered geometry of the NW mat scatters light causing a photon to interact with multiple nanowires increasing the probability that it will be absorbed by the a-Si cell coating the nanowires. Thus the NW mat makes it possible to improve the effective absorption efficiency of the cell without increasing the cell thickness and compromising the carrier collection efficiency. We fabricated and studied these disordered nanowire structures. The mats are grown using the VLS technique with nanowire lengths of 5-10 microns. The nanowires are coated with 100-200 nm a-Si PIN solar cell structures. Top contact is achieved by using a transparent conducting oxide. We discuss optical characterization data exploring how different NW mat geometries can be used to enhance light absorption. We present spectral response curves and current-voltage characteristics of NW mat based photovoltaics to demonstrate how mat geometries can be optimized to affect cell performance. Our experiments focus on device geometries that can be fabricated using techniques that are compatible with a-Si processing technologies.

Read more from SRI