Piacentino, M.R.; van der Wal, G.S.; Hansen, M.W., “Reconfigurable elements for a video pipeline processor,” Field-Programmable Custom Computing Machines, 1999. FCCM ’99. Proceedings. Seventh Annual IEEE Symposium on, vol., no., pp.82,91, 1999
Abstract
This paper describes a family of reconfigurable processing elements (RPEs) used to support video processing for the Sarnoff Vision Front End 200 (VFE-200) vision system. Within the VFE-200 RPEs have been used to estimate visual motion, compute 3D scene structure using stereo analysis, perform geometric transformations (warps) on imagery with interpolation, and to act as triple ported frame store memory units. The RPEs described in this paper incorporate complex DRAM memory control interfaces, high precision fixed- and floating-point arithmetic (including floating point division), and sophisticated hybrids of memory and computational functions. Within this paper, the architecture and implementation of the RPEs and the VFE-200 are described, and examples of how the RPEs are used to support specific computer vision functions at real-time video rates are presented