Senior Principal Research Scientist, Vision Systems Laboratory
Gooitzen van der Wal, a senior principal research scientist in SRI’s Vision Systems Laboratory, has more than 34 years of experience in real-time system and chip design and advancing the state-of-the-art in vision technologies.
Specializing in low-power, high-performance, embedded vision systems, van der Wal was the principle architect for the Acadia® I and Acadia II application-specific integrated circuits (ASICs) sponsored by the Defense Advanced Research Projects Agency (DARPA). Key vision functions of the Acadia chips are multi-resolution based low-latency multi-spectral fusion, contrast enhancement, image stabilization, video tracking, and computing depth from stereo cameras. Current projects involve hybrid architectures for a range of vision systems using a variety of processing platforms including the Acadia chip, field-programmable gate arrays (FPGAs), multi-core processors, and smartphone/tablet processors.
Van der Wal received his bachelor’s and master’s degrees in electrical engineering at Twente University, Netherlands. He started his career designing the RCA Telephone Codec chip at RCA Laboratories, in what is now SRI’s Princeton, NJ, location. He is a member of IEEE, has received 10 RCA/Sarnoff Achievement Awards, holds 18 U.S. patents, and has authored/co-authored 25 professional publications and presentations.
Publications
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Low-Power In-Pixel Computing with Current-Modulated Switched Capacitors
We present a scalable in-pixel processing architecture that can reduce the data throughput by 10X and consume less than 30 mW per megapixel at the imager frontend.
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Real-Time Hyper-Dimensional Reconfiguration at the Edge using Hardware Accelerators
In this paper we present Hyper-Dimensional Reconfigurable Analytics at the Tactical Edge using low-SWaP embedded hardware that can perform real-time reconfiguration at the edge leveraging non-MAC deep neural nets (DNN) combined with hyperdimensional (HD) computing accelerators.
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Hyper-Dimensional Analytics of Video Action at the Tactical Edge
We review HyDRATE, a low-SWaP reconfigurable neural network architecture developed under the DARPA AIE HyDDENN (Hyper-Dimensional Data Enabled Neural Network) program.
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Fast, Full Chip Image Stitching of Nanoscale Integrated Circuits
In this paper, we describe the algorithmic steps taken in the processing pipeline to quickly create a global image database of an entire advanced IC.
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FPGA acceleration for feature based processing applications
In this paper, we describe the implementation of an algorithm that combines distributed feature detector (D-HCD) with a rotational invariant feature descriptor (R-HOG).
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An Embedded Vision Services Framework for Heterogeneous Accelerators
This paper describes an architecture framework using heterogeneous hardware accelerators for embedded vision applications.